(1) Field of the invention
The present invention relates to a hierarchical data transmission system in which a plurality of data trains are multiplexed and transmitted from a transmitter side thereof and the thus transmitted data trains are received at a receiver side thereof and demultiplexed therein to reproduce the original data trains.
A hierarchical data transmission system basically comprises a side for dealing with data of a low order group and a side for dealing with data of a high order group. The high order group of data is produced by summing at least two low order groups of data, so that the high order group of data provides a very high transmission rate, and accordingly, the high order group contains a great amount of data.
(2) Description of the related art
A current optical fiber data transmission system has realized such ultra-high speed data transmission as 405 Mbps or 810 Mbps and a multiplexing apparatus is put into practical use in order to obtain such ultra-high speed data at the high order group signals.
In such a multiplexing apparatus, a plurality of low order group data trains are multiplexed into a plurality of intermediate speed data trains. Thereafter, these intermediate speed data trains are further multiplexed into high order group data trains. This procedure is also employed for demultiplexing the high order group data train. Such multiplexing apparatus can be mounted into an LSI unit of the function corresponding to the data transmission rate.
In such a case, an LSI for processing high order group data trains operates with a high speed clock signal, an LSI for processing intermediate data trains operates with an intermediate speed clock signal, and an LSI for processing low order group data trains operates with a low speed clock signal.
The low speed clock signal in the LSI for processing low order group data trains can be formed by the frequency division of the intermediate speed clock signal in the LSI for processing the intermediate data trains, and this intermediate speed clock signal can be formed by the frequency division of the high speed clock signal in the LSI for processing the high order group data trains.
FIG. 1 is a block diagram illustrating the structure of the multiplexing apparatus described above, while FIG. 2 is a timechart which indicates operation timings of respective portions.
The multiplexing apparatus of FIG. 1 multiplexes the 9-channel low order group data trains of 45 Mbps and outputs high order group signals of 405 Mbps. For multiplexing, the low order group data train of each channel, as the main signal, is synchronized to form a frame. Moreover, a frame synchronization signal and service channels for monitor and control which form subsignal must be inserted. These processings cannot be realized easily for the ultra-high speed data train as high as 405 Mpbs. Therefore, as shown in FIG. 1, the three intermediate speed data trains of 135 Mbps are respectively generated by multiplexing the 3-channel low order group data trains the synchronization signal of each channel and service channels are inserted at this stage, and thereafter the three intermediate speed data trains are interleaved to output the high order group data train of 405 Mbps.
In FIG. 1, the high speed operation clock of 405 Mbps is supplied, from the oscillator 4, to the multiplexing circuit MUX2 which generates the high order group data trains of 405 Mbps, and the intermediate speed operation clock of 135 Mbps which as been obtained by dividing the high speed clock sent from OSC 4 into 1/3 with a frequency divider F-DIV5 is supplied to the multiplex circuit MUX1 which generates the intermediate speed data trains of 135 Mbps. Moreover, the intermediate speed clock sent from F-DIV5 and a low speed operation clock of 45 Mbps which is obtained by dividing said intermediate speed clock into 1/3 with the frequency divider F-DIV6 is supplied to the interface circuits 11.about.19 for the low order group data trains of CH1.about.CH9. The data train service channels (for monitoring and controlling the transmitting lines and repeaters of 405 Mbps) to be multiplexed together with the low order group data trains (CH1.about.CH9) is 710 kbps, in this case, and this data train for service channels can be generated by multiplexing the low order group data trains of 11 channels of 64 kbps by the multiplexing circuit for service channel S-CHMUX3. The low speed operation clock for S-CHMUX3 can be obtained by dividing the low speed clock sent from F-DIV6 into 1/64 with the frequency-divider F-DIV7.
Interface 11.about.19 and S-CHMUX3 output a bit position information (timing signal) which is required for multiplexing at MUX1, MUX2 and this bit position information is input to MUX1 and MUX2. Namely, the multiplexing circuits MUX1, MUX2, S-CHMUX3 and interface circuits 11.about.19 are operating under the synchronized condition and the clock signal supplied from OSC4, F-DIV5, 6, 7 is the reference signal for such synchronization.
Here, as explained above, MUX1, MUX2, S-CHMUX3, interface circuits 11.about.19 are respectively mounted to LSI's and the clock signal is supplied from an external circuit. Since respective LSI's must be operated synchronously, although the operation speeds of LSI's are quite different, the clock obtained by sequentially dividing the reference clock of OSC4 is used as the clock signal.
However, the structure illustrated in FIG. 1 is accompanied by the following problems.
In case the high speed reference clock output from OSC4 like FIG. 1(1) is divided by F-DIV5, it is affected by the delay in signal propagation and operation of F-DIV5, so that an output of F-DIV5 is delayed by "a" in the phase (the rise timing of clock) in comparison with an output of OSC4 as shown in FIG. 2(2). Moreover, an output of F-DIV6 obtained by dividing an output of F-DIV5 is delayed, as shown in FIG. 2(3), by a+b in the phase in comparison with an output of OSC4, because delay (b) is accumulated. A delay in signal propagation and operation of interface circuit 11 is further accumulated in the CH1 timing signal 111 which is generated based on the clock signal sent from F-DIV6, so that the output of interface circuit 11 is delayed by "a+b+c" in the phase in comparison with an output of OSC4 as shown in FIG. 2(4). Similarly, the delay (b') is accumulated on an output of F-DIV7 obtained by dividing an output of F-DIV6 as shown in FIG. 2(5) and the delay (c') is also accumulated on the service channel timing signal 133 generated based on the clock sent from F-DIV7 and is output from S-CHMUX3 as shown in FIG. 2(6). Furthermore, in the timing signal based on the timing signals 111, 133 generated by MUX1, the delay (d) in propagation of signal and operation of MUX1 is accumulated to the delay (a+b"+c"), as shown in FIG. 2(7), which includes the influence of both delay (a+b+c) of an output of interface circuit 11 and delay (a+b+b'+c') of an output of S-CHMUX3. Finally, further the delay (e) is accumulated, as shown in FIG. 2(8), to the timing signal used within MUX2 which generates the high order group data train.
Therefore, as shown in FIG. 2(9), the timing signal used by MUX2 allows accumulation of a delay of (a+b"+c"+d+e) in comparison with the phase of reference high speed clock of OSC4. As shown in FIG. 2(9), MUX2 outputs the high order group data train 1 , 2 , 3 . . . in synchronization with the high speed clock (output of OSC4), but as shown in FIG. 2(8), when the timing signal used within MUX2 is delayed by (a+b"+c"+d+e) in comparison with the phase of high speed clock and when (a+b"+c"+d+e)&gt;T (T is a period of high speed clock), the signal 1' is output in the timing where the signal 2 should be output. Therefore, the normal multiplex processing cannot be realized within MUX2.
In the case of demultiplexing the high order group data train into a plurality of low order group data trains, only the transmission direction of the high order group data train of 405 Mbps, intermediate speed data trains of 135 Mbps, low order group data train of 45 Mbps and service channel data train of 0.7 Mbps is reversed in FIG. 1 and the same structure is employed for the clock signal and timing signal. Therefore, this structure has a problem similar to that of the foregoing multiplex apparatus.
Above problems are generated, in the multiplex apparatus for ultra-high speed data train which sequentially multiplexes the low order group data trains in a plurality of stages, because the delay times are accumulated by sequentially dividing the reference high speed clocks for the LSI having a plurality of processing speeds.